The present invention relates generally to a vertical transistor and a method for forming the same, and more particularly, to a vertical transistor with improved operation speed and a method for forming the same.
Various technologies are used to form a transistor in a semiconductor device. One such technology that currently has wide use is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Typically, a semiconductor substrate will be divided into a peripheral region and a cell region, and MOSFETs are formed on the respective regions of a semiconductor substrate. A typical MOSFET includes a stacked structure of a gate insulation layer and a gate conductive layer. The gate conductive layer is generally formed of a polysilicon layer or a stacked layer including a polysilicon layer and a metal layer.
Trends in the semiconductor industry have lead to a reduced design rule, and the semiconductor industry is constantly pursuing an enhanced degree of integration of semiconductor devices while increasing the operation speed and the yield of the semiconductor devices.
Vertical transistors are often suggested as a device capable of overcoming the current limitations (such as the capability of a high level of integration and limitations in current characteristics) of existing transistors.
Unlike the existing transistor, which includes a gate and source/drain regions formed in a substrate at respective sides of the gate thereby having a horizontal channel, the vertical transistor includes a gate and source/drain regions formed above and below the gate respectively, and thereby, the vertical transistor is formed with a vertical channel.
A typical vertical transistor having a vertical channel is formed in a manner such that a pillar type active pattern extends vertically to a main surface of the semiconductor substrate, an annular gate is formed so that the annular gate surrounds a lower end portion of the pillar type active pattern, and the source region and the drain region are respectively formed above and below a channel unit of the pillar type active pattern surrounded by the annular gate.
This vertical transistor can be advantageously employed in highly integrated devices, since the vertical transistor has an increased current and a decreased size.
However, the conventional vertical transistor described above has the inevitable problem of increased parasitic capacitance since the gate structurally surrounds the pillar type active pattern. One particular disadvantage is the deterioration of current properties caused by the increase in the parasitic capacitance, which in turn causes a problem of RC delay. Also, an additional complication exists in that the operation speed is lowered by the parasitic capacitance when the vertical transistor is employed in an NMOS having a relatively large depletion ratio of a polysilicon layer.